ASIC (Application Specific Integrated Circuit) components fabricated in older semiconductor processes were designed to operate at higher power supply voltage (5 volts was the standard power supply voltage for many years). However, ASIC components designed for use in newer semiconductor processes can only support lower operating power supply voltages (3.3 volts or lower). In a large number of system applications, components in the older and newer processes communicate with each other. Consequently, ASICs that are in systems that can only support lower power supply voltages need high voltage tolerant input and/or output driver circuits. In the prior art, high voltage tolerant off chip driver circuits have drawbacks such as high leakage from output pad to ground or power supply, over-stressing of transistor junctions because of high voltage external signal levels, and increased transition delays and excessive power dissipation.
An example of a prior art off chip driver circuit is disclosed in U.S. Pat. No. 5,151,617. A circuit diagram from that patent is reproduced herein as FIG. 1. This design operates at 3.3 volts power supply (Vdd), and it communicates with another design, which produces a 0 to 5 Volt signal level at the common node (Output Pad) of the two drivers. While this design protects all the transistors in the circuit from being over stressed by an external 5 volt signal, it has its shortcomings.
In active mode when the driver input switches from high to low level, outputs of the pre-driver circuit, nodes 1 and 2, switch from low to high. Initially the transmission transistor Tp1 is ‘Off’ and transistor Tn1 is ‘On’. Tn1 produces a voltage (Vdd−Vtn) at the gate of the p-channel pull-up transistor Tp3, which stays partially ‘On’ until driver output reaches well below (Vdd−Vtp). Vtn and Vtp are the threshold voltages of the n-channel and p-channel transistors respectively. This condition results in longer high to low transition time. During high to low transition, n-channel pull down transistor Tn3 turns on faster and p-channel pull up transistor Tp3 takes a longer time to turn ‘Off’ completely, which results in high short circuit or flush through current from Vdd to ground through the pull-up and pull-down transistors for a longer time. This short circuit current causes higher power dissipation. This power dissipation is due to higher current drawn by the circuit in its operation and will require a larger power supply and produce a higher module and circuit board temperature.
When the driver circuit in FIG. 1 is in a high impedance mode and its output is higher than Vdd due to an external signal, Tp2 turns on and provides higher voltage at the gate of transistor Tp3 and turns Tp3 off so that no current flows through Tp3 to Vdd from the external source. Since transistor Tn2 is in series with transistor Tn3, the external high voltage is reduced to below (Vdd−Vtn) across Tn3. Transistor Tp4 generates bias for the Nwell region in which transistors Tp1, Tp2, and Tp3 are formed.
The art would therefore benefit from an off chip driver circuit that has high performance and low power dissipation.